CPU progress already stopped. All this is bad news.

@Ralth_B

To make thing simple - in early processes all elements scaled proportionally. Already at around 28mm it started to become hard, transistors design changed and only some elements had been scaled while other remained larger. In 14nm it became even worse, 14nm from different manufacturers can differ very much in size. Now 14nm is mostly marketing term.

@Ralth_B

In what regard exactly?

They can no longer scale in frequency so they add cores keeping very big margins.

Most people do not understand that 8x core chip cost to Intel is around 1.5-1.7x compared to more common 4 core chip. So, managers in Intel and press keep people in dark to get big margins and advertisement budgets that come from this same margins.

@Ralph_B

It is not about CPU, it is about Intel 14nm process. I suggest to check specialized resources like EE Times

http://www.eetimes.com/document.asp?doc_id=1329279

And here is another issue

Sales for the month of June 2016 reached US$26.4 billion, an uptick of 1.1% over the May total of US$26.1 billion, but down 5.8% from the June 2015 total of US$28.0 billion, SIA said. Cumulatively, year-to-date sales during the first half of 2016 were 5.8% lower than they were at the same point in 2015.

With exponentially rising costs of development and manufacturing costs it is not good to have any sales drops.

Skynet will just have to wait.

Samsing 10nm PR

Following the successful mass production of the industry’s first FinFET mobile application processor (AP) in January, 2015, Samsung extends its leadership in delivering leading-edge process technology to the mass market with the latest offering.

“The industry’s first mass production of 10nm FinFET technology demonstrates our leadership in advanced process technology,” said Jong Shik Yoon, Executive Vice President, Head of Foundry Business at Samsung Electronics. “We will continue our efforts to innovate scaling technologies and provide differentiated total solutions to our customers.”

Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption. In order to overcome scaling limitations, cutting edge techniques such as triple-patterning to allow bi-directional routing are also used to retain design and routing flexibility from prior nodes.

The slower the progress - the more PR you need.

There is evidence that linear scaling has already reached its physical limits. “People say they are doing 10nm process modes, but you will not find any line widths at that level,” Lu says.

That’s why technology development has gone non-linear. In 2011, Intel announced its Tri-gate technology, leading the way from planar development of transistors on silicon into three dimensions. With 3D, even scaling by a factor of 0.85 results in a transistor density that is more like 0.5 scaling in two dimensions, Lu says.

Other companies have followed that trend. Toshiba built 3D NAND in 48 layers, and that memory has been used in Apple’s iPhone 7. Samsung has taken the idea a step further with the creation of a 64-layer flash memory device. The technology level was only 32nm, yet it was the virtual equivalent of 13nm, Lu notes.

“Now we are in silicon age 2.0 with vertical transistors and a scaling parameter of 0.8 to 0.85,” Lu says. “Silicon 3.0 is like a 3D landscape. We are seeing more and more people going there.”

Lu says that his theory, as described in his paper, starts with Silicon 4.0. The advances from the current 3.0 generation have enabled a lot of new applications such as augmented reality, virtual reality and machine intelligence, he says. The next threshold is what Lu calls heterogeneous integration, or the incorporation of silicon and non-silicon materials by means of technologies such as integrated fan out (InFO).

http://www.eetimes.com/document.asp?doc_id=1330750

Note that flip chip shown on the left is widely used in cameras for long.

As the global semiconductor industry moves into the 7nm process, there are only four companies that can offer related products, Globalfoundries, TSMC, Samsung and Intel, of which two are pure-play foundries. We value much the 7nm process believing that this process will be a very important and long-living technology for the semiconductor industry; we have already secured a number of clients and we have great confidence in the 7nm process race.

We decided to jump from 14nm to 7nm directly, while skipping the 10nm process because we believe that 10nm will help not much to improve power consumption and costs for clients; the 10nm node is more like a semi-generation process, similar to the previous the 20nm technology, which could not meet clients' requirements.

http://www.digitimes.com/news/a20161102PD203.html

Both Taiwan Semiconductor Manufacturing Company's (TSMC) and Samsung's 10nm processes have reached lower-than-expected yield rates, according to industry sources. Yield rates for TSMC's 10nm process technology are not what the foundry expected, the sources said.

Yield rates for Samsung's 10nm process technology have been low prompting Qualcomm to turn cautious about its product roadmap for 2017, the sources said. Qualcomm originally planned for the Snapdragon 835 and other chips including the 660 (codenamed 8976 Plus) built using Samsung's 10nm process, but has revised its roadmap by having only the 835-series made using the newer node technology.

When a manufacturer converts from standard lithography to a double-patterning approach the lithography tool resolution is relaxed, and this shows on the chart’s top blue line. This line shows the lithography requirements for each process. A 45nm process uses 45nm lithography. Since 35nm uses double-patterning, then the lithography backs off to 70nm, and the 25nm process uses 50nm lithography. At 16nm, since quadruple patterning is used, lithography backs off to 4 x 16nm = 64nm.

SDAP limit is around 19nm btw

I don't understand this slide, supposedly showing the 3-year process advantage Intel has: http://images.anandtech.com/doci/11115/C4PU6KzWMAEglWH_575px.jpg

The 3-year gap they show is comparing Intel's 14nm process to competitors 10nm process. So is Intel saying that their 14nm process achieves higher density than the 10nm process from Samsung and others? And if so, how is this possible?