Intel 10nm pushed to 2022 at least (most probably it is total toast)

Leaked roadmaps from Dell people.

Next year Intel plans to add another 2 cores while keeping same deficient double channel memory system, and this time thermal throttling will be real severe.

Major issues

Recent reports indicate that the 7nm node is expensive, thus leading several large players to scale back product development on leading nodes, thus leaving about 10 percent of TSMC’s 7nm production capacity underutilized.

Strange reports.

Notes from SemiAccurate's CC about Intel

• Cannon Lake 10 nm, "launched" in 2017 with a single Lenovo China laptop, had single digit yields
• Charlie reported a "level of fear he had never seen" around then from Intel sources [Similar to Olympus]
• The original plan was for four fabs to move to 10 nm. 3 out of the 4, including one in each of Israel, Arizona, and Oregon, will NOT move to 10 nm.
• No info on what the 4th fab is doing, but at least 75% of the original 10 nm fab capacity is no longer there.
• COAG (Contact Over Active Gate) was to have saved INTC 10% in area. It completely failed, impacting integrated graphics. This is why the Q4 2017 10 nm Canon Lake had no iGPU
• 10nm is slower, and its yields are < 50% that of 14 nm.
• The recently leaked Dell roadmaps confirm that the INTC 2017 claim that 10 nm and 10nm+ processes will be behind on performance compared to 14 nm.
• Ice Lake 10 nm will only be the low performance end of the stack. It will also come in 14 nm variants.
• High core count and performance as well as AI with Bfloat 16 will remain at 14 nm.
• All INTC custom foundry customers have bailed, including Cisco, Panasonic, and LG. The entire INTC custom foundry effort was a flaming disaster.

• Questioned about INTC 14 nm shortages, Charlie mentions (previously behind the paywall) that this was driven by massive hits to server customers from Spectre and Meltdown security flaws, which drove volume buys to restore capacity [China buys ahead of tariffs in Intel speak].

So, this diversion played well.

• AMD Rome delivers a 1.6x performance delta over INTC's current and for the next year Cascade Lake.
• AMD will have a 50 to 60% server CPU performance advantage until at least late 2021.
• AMD Milan will have an amazing 15 chiplets.
• AMD is pushing chiplets very hard.

From https://www.reddit.com/r/AMD_Stock/comments/bll3pp/notes_from_semiaccurates_cc_with_susquehanna_this/

Intel started to think about separating factories

While during recent meeting they told that no such plans this year exist, but they also told that they will return to such option within 2020. If we will see 10nm/7nm still not working we can see extremely fast and sudden merger or separation. So, such we can be already to only 2 companies competing in 2021 (Samsung and TSMC).

How slowing down progress look at supercomputers chart

Same as 2011 had been year of 2500K, 2019 is the year of Ryzen 3xxx, and will be next peak before even faster reduction. Industry won't be able to scale further from 16 cores without drastic price increases and thermal output increase.

“It's going to keep going,” said Jim Keller, a semiconductor rock star who joined Intel last year as senior vice president of silicon engineering, and a cohost of the event. “Moore’s law is relentless”

“The working title for this talk was ‘Moore’s law is not dead but if you think so you’re stupid,’" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore’s law. “I’m not pedantic about Moore’s law talking just about transistors shrinking—I’m interested in the technology trends and the physics and metaphysics around that,” Keller says. “Moore’s law is a collective delusion shared by millions of people.”

Keller said Sunday that Intel can sustain that delusion, but that smaller transistors will be just one part of how. On the conventional side, he highlighted Intel’s work on extreme ultraviolet lithography, which can etch smaller features into chips, and smaller transistor designs based on nano-scale wires due to arrive in the 2020s.

Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. “That’s basically already working,” he said.

All this vertical 3D stuff does not work for heavy load chips like CPUs. Only for their SRAM and IO parts may be.

Interesting slides

How it looks in smartphone space

With rising heat dissipation demand from major vendors including Samsung Electronics, LG Electronics, Huawei, Oppo and Xiaomi for their 5G smartphones, half of cooling module shipments for smartphones in the second half of 2019 will be vapor chamber-based solutions, and the other half heatpipe-based ones, according to industry sources.

And it is only small beginning.

Fall of smartphone huge market will be unprecedented and it will destroy some of leading semiconductors manufacturers.

3nm marketing nanometers will be tough

This week, at its technology forum ITF USA 2019, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a dual-damascene 21nm pitch test vehicle relevant for manufacturing the 3nm logic technology node. With this test vehicle, a 30 percent improvement in resistance-capacitance product (RC) was obtained compared to previous generations, without impacting reliability. The need for implementing scaling boosters such as self-aligned vias and self-aligned blocks in 3nm and beyond interconnect technologies has been demonstrated.

Moore’s Law has run out of gas, “and that is profound,” said Victor Peng, CEO of Xilinx.

“You can get one of the three, it’s hard to get two of three, and I would challenge anyone who says they can get three of the three,” he said. Today’s extreme ultraviolet (EUV) lithography systems only remove the complexity of multi-patterning today’s chips, the 7-5-3-nm names of the latest nodes “are all marketing numbers, and no one has fixed the interconnect problem.”

“The cost of designing a 5-nm chip will be astronomical,” limiting the node’s use to a few companies who “can amortize it across multiple designs. Because of the constraints of Moore’s Law, you have to work harder — there’s no freebie in optical scaling anymore.”